1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to forming lead-free solder bumps on a contact layer of a semiconductor chip.
2. Description of the Related Art
In the manufacture of modern integrated circuits, it is usually necessary to provide electrical connections between the various semiconductor chips making up a microelectronic device. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wirebonding, tape automated bonding (TAB), flip-chip bonding, and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to substrates, carriers, or other chips by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry. In flip-chip technology, solders balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip comprising a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package, each of which corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier package, are then electrically connected by “flipping” the semiconductor chip and bringing the solder balls into physical contact with the bond pads, and performing a “reflow” process so that each solder ball bonds to a corresponding bond pad. Typically, hundreds, or even thousands, of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips, and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
Historically, the materials used for forming solder balls used in flip-chip technology have included any one of a variety of so-called tin/lead (Sn/Pb) solders. In most commercially-used Sn/Pb solder alloys, the amount of tin (Sn) may vary from approximately 5% atomic weight up to approximately 70% atomic weight, with the balance of the solder alloy being lead (Pb). Furthermore, the melting temperatures of Sn/Pb solder alloys will vary according to the exact alloy make-up, a factor which has some influence on overall processing parameters. In the semiconductor processing industry, the most common Sn/Pb solders are 5/95 solders (i.e., 5% tin and 95% lead), 60/40 solders (i.e., 60% tin and 40% lead), and 63/37 solders (i.e., 63% tin and 37% lead, or so-called “eutectic” mixture). Eutectic Sn/Pb solder has an advantage of having the lowest melting temperature of the Sn/Pb solders (183° C.) which is truly a point, rather than a range, as may be exhibited by other non-eutectic Sn/Pb alloys.
In recent years, however, manufacturing industries have generally moved away from the use of Sn/Pb solders in most commercial applications, including semiconductor processing. Accordingly, lead-free soldering materials, such as Sn/Ag (tin-silver), Sn/Cu (tin-copper), Sn/Ag/Cu (tin-silver-copper, or SAC) solders, and the like, have been developed as substitute alloys for forming solder bumps. However, these substitute soldering materials generally may have a slightly higher melting temperature than most of the commonly-used Sn/Pb solders. Furthermore, at least some of these lead-free solder materials exhibit other process-related difficulties that must be addressed during semiconductor device manufacturing, as will be discussed in further detail below.
FIG. 1 is a process flow diagram that illustrates the various sequence of steps involved in forming lead-free solder bumps in accordance with one prior art solder bump process. In general, the illustrative prior art process sequence shown in FIG. 1 includes a first process step 110 wherein an underbump metallization (UBM) layer is formed, after which, in process step 120, a resist mask is formed in advance of performing a solder plating process in step 130. Thereafter, the resist mask is stripped in process step 140, the UBM layer is etched in process step 150, and finally, a solder bump reflow process is performed in process step 160. Each of the process steps identified in FIG. 1 and described in a general fashion above is illustrated in respective FIGS. 1a-1f, which will now be described in detail below.
FIG. 1a schematically illustrates the process step 110 of FIG. 1, wherein an underbump metallization (UBM) layer 104 is formed. The underbump metallization layer 104 may be formed on a patterned passivation layer 103, which may in turn be formed above a last metallization layer 101 of a semiconductor device 100. Depending on overall device architecture requirements, the semiconductor device 100 may comprise a plurality of integrated circuit elements, such as transistors, capacitors, resistors, conductive lines, contact elements, and the like. Additionally, the patterned passivation layer 103 may include an opening 103a that is positioned to expose a conductive contact pad 102 that is formed in the upper portion of the last metallization layer 101, which may provide electrical contact to one or more the plurality of integrated circuit elements of the semiconductor device 100.
As shown in FIG. 1a, the UBM layer 104 may be formed in a substantially conformal manner above the patterned passivation layer 103 so as to cover the exposed upper surface of the conductive contact pad 102, the sidewall surfaces of the opening 103a, and the upper surfaces of the passivation layer 103. Depending on overall process flow and device requirements, the UBM layer 104 may include a plurality of individual layers, each of which may be individually adapted to provide the requisite adhesion, barrier, protection, and conductivity characteristics of the overall UBM layer 104. For example, the UBM layer 104 may include, but not necessarily be limited to, a titanium-tungsten/chromium-copper/copper (TiW/CrCu/Cu) layer stack, a chromium/chromium-copper/copper (Cr/CrCu/Cu) layer stack, a titanium-tungsten/copper (TiW/Cu) layer stack, a titanium/copper/nickel (Ti/Cu/Ni) layer stack, a titanium-tungsten/nickel-vanadium/copper (TiW/NiV/Cu) layer stack, and the like, wherein the final copper layer may serve as a current distribution layer in a later-performed electroplating process (see process step 130 and FIG. 1c). The UBM layer 104 may be formed by an appropriately designed deposition sequence 111, which, may include a sputter deposition process, a chemical vapor deposition (CVD) process and the like, or a combination of these processes, depending on the material types and the number of layers used.
FIG. 1b schematically illustrates the semiconductor device 100 of FIG. 1a during a subsequent manufacturing step. More specifically, FIG. 1b shows process step 120 of FIG. 1, wherein a patterned resist mask 105 is formed above the UBM layer 104. Depending on the desired integration scheme, the patterned resist mask 105 may be formed by a process sequence 121 that includes a plurality of steps based on traditional photolithography techniques well known to those having skill in the art. As shown in FIG. 1b, the patterned resist mask 105 may include an opening 105a formed above the opening 103a in the patterned passivation layer 103, thereby defining the position and initial shape of the solder bump 106 in the as-plated condition, as will be described more fully below.
As schematically illustrated in FIG. 1 c, further processing of the semiconductor device 100 of FIG. 1b is continued during process step 130, wherein a lead-free solder bump 106 is formed in the openings 103a and 105a of the patterned passivation layer 103 and resist mask 105, respectively. As previously noted, the underbump metallization layer 104 may act as a current distribution layer during an electrochemical deposition process 131, such as an electroplating process, thereby facilitating the electrochemical deposition of the solder material used to form the solder bump 106. The solder bump material may be any one of several lead-free solder materials known in the art, such as Sn/Ag, Sn/Cu, Sn/Ag/Cu (SAC), and the like. Furthermore, depending on the device requirements and/or the desired processing scheme, the solder bump 106 may be formed on an underlying pillar comprising electrochemically deposited copper (Cu) or nickel (Ni), and the like. For example, in at least one embodiment, the solder bump 106 may be formed on a nickel pillar, and may be made up of a tin/silver (Sn/Ag) alloy solder material having a silver content in the range of approximately 1.8% to 3.0% by weight, whereas the balance of the solder alloy may be substantially tin. Depending on various processing considerations, such as reflow temperatures and the like, other weight percentages of silver and/or copper, in combination with tin, may also be used.
FIG. 1d schematically illustrates the semiconductor device 100 of FIG. 1c during the process step 140 shown in FIG. 1, wherein the patterned resist mask 105 is removed from above the UBM layer 104. As shown in FIG. 1d, a resist strip process 141 may be performed so as to selectively remove the patterned resist mask 105 relative the materials of the underbump metallization layer 104 and the as-plated solder bump 106. Depending on the desired processing strategy, the resist strip process 141 may be, for example, a wet chemical strip process or a dry etch process, recipes for which are well known in the art. During process step 150, the UBM layer 104 may be patterned so as to electrically isolate the solder bump 106 from other adjacent solder bumps that may have been simultaneously formed during the process sequence described by process steps 110-140. As shown in FIG. 1e, the UBM layer 104 may be patterned by performing an etch sequence 151, which, depending on the number and material variety of any sub-layers that may make up the UBM layer 104, may include a plurality of wet and/or dry etch techniques.
Thereafter, the substrate comprising the semiconductor device 100 may be transported to a furnace tool (not shown) where the bump reflow process step 160 will subsequently be performed. However, prior to loading the substrate comprising semiconductor device 100 into the furnace tool (not shown), the device 100 may be exposed to ambient atmospheric conditions, during which time a native tin oxide layer 107 may be formed on the exposed surface of the newly formed solder bump 106, as shown in FIG. 1e. 
During the bump reflow process step 160, the semiconductor device 100 of FIG. 1e may be exposed to a reflow process 161, which, as shown in FIG. 1f, transforms the solder bump 106 of FIG. 1e into a substantially rounded solder ball 108. The reflow process 161 may be performed in a programmable oven or furnace having, for example, resistive heaters or infrared (IR) lamps, and, depending on the composition of the solder material comprising the solder bump 106, may be performed at reflow temperatures in the range of approximately 200-300° C. For example, for Sn/Ag solder bumps having a silver content in the range of 1.8-3.0 weight percent, the reflow process 161 may be performed between approximately 225° C. and 250° C. Additionally, the reflow process 161 may be performed for a duration as may be appropriate for the specific solder material composition so as to improve the overall uniformity of the solder alloy material, and, furthermore, to diffuse solder bump material into the UBM layer 104, thereby forming intermetallic compounds that may provide the rounded solder ball 108 with high mechanical toughness.
As noted above, a native tin oxide layer 107 may have formed on the exposed surface of the solder bump 106 between process steps 150 and 160. This native tin oxide layer 107 is typically removed during the reflow process 161 so that an oxide layer will not be present on the surface of the reflown solder ball 108. Accordingly, the reflow process 161 may be performed in a substantially reducing ambient that is adapted to remove any native tin oxide layer 107 that may be present on the exposed surface of the solder bump 106. In certain embodiments, the reducing ambient may comprise gaseous formic acid (CH2O2), which removes the native tin oxide layer 107 during the reflow process 161 by chemically reacting with the tin oxide (SnO) on the surface of the solder bumps 106 to form tin byproducts, such as Sn(CHO2)2 (tin II formate) and the like.
It should be further noted, however, that during normal substrate processing, a significant wait time may occur between process step 150 (UBM etch) and process step 160 (bump reflow), which may sometimes be on the order of several hours, or even up to a day or more. While such extended wait times, and the commensurate lengthy exposure of solder bumps to ambient conditions, were not normally detrimental to tin-lead (Sn/Pb) solder bumps, the surface oxidation rate of solder alloys having a very high weight percentage tin concentration (such as Sn/Ag solders) may be significantly higher than that of the typical Sn/Pb solders. As such, the amount of tin oxide that must be removed from the surface of solder bumps 106 made of Sn/Ag alloy solders is proportionately greater. Moreover, any tin byproducts that are formed during the reflow process 161 may have a tendency to deposit preferentially on the inside surfaces of the furnace tool and exhaust lines and, over time, may flake off of these surfaces and re-deposit as particle defects 109 on the exposed surfaces of the device 100, including the reflown solder ball 108, as shown in FIG. 1f. These particle defects 109 may also interfere with the electrical connection that is obtained between the solder balls 108 on a semiconductor chip and the bond pads on a package carrier, thereby potentially reducing device reliability. To avoid the occurrence of such particle defects 109, the furnace tool where the reflow process 161 is performed must be periodically cleaned on a regular basis.
On the one hand, device reliability may be increased by increasing the tool cleaning frequency—i.e., shortening the tool cleaning cycle—however, at the expense of tool downtime and the corresponding decrease in overall productivity. On the other hand, productivity may be increased by reducing the tool cleaning frequency—i.e., lengthening the tool cleaning cycle—however, at the expense of increased particle defects and a corresponding decrease in overall device reliability. Accordingly, and in view of the foregoing, there is a need to implement new design strategies to address the manufacturing issues associated with forming lead-free solder bumps on semiconductor chips. The present disclosure relates to process schemes that are directed to avoiding, or at least mitigating, the effects of one or more of the problems identified above.